In recent years, a multilayer wiring structure has been more widely adopted for a semiconductor device as the size of the semiconductor device is increasingly reduced. As shown in a plan view in FIG. 10 and a cross-sectional view in FIG. 11 along the line A-A in FIG. 10, the multilayer wiring structure has a lower-layer wiring line 33 insulated by interlayer insulating films 32 and 34 on a substrate 31. Above the lower-layer wiring line 33, upper-layer wiring lines 35 are disposed so as to intersect with the lower-layer wiring line 33. With such a multilayer wiring structure, a layout design can be made easier and an area for chips can be smaller, but because the upper-layer wiring lines 35 are disposed so as to cross over a level difference section made by the lower-layer wiring line 33, a problem of a short circuit between the upper-layer wiring lines 35 occurs. In particular, when the upper-layer wiring lines 35 are arranged so as to intersect with the level difference section made by the lower-layer wiring lines 33 with narrow intervals, the wiring lines become more susceptible to a short circuit.
This problem is caused by anisotropic dry etching that is employed in a recent wiring forming process. Although the anisotropic dry etching makes it possible to form the wiring lines precisely according to a resist pattern, when the thickness of a metal film used to form the upper-layer wiring lines is increased due to a large level difference, a part of the metal film is not removed in the etching, and is left as an etching residue. The smaller the inter-wiring space becomes, the more likely this problem is to occur.
In a conventional multilayer wiring structure, for example, when the upper-layer wiring lines 35 are disposed so as to cross over the level difference section made by the lower-layer wiring line 33, an etching residue 36 of the upper-layer wiring lines 35 would be left along the level difference section on the lower-layer wiring line 33. When the etching residue 36 is connected between the respective upper-layer wiring lines 35, the short circuit occurs.
In order to solve the short-circuit problem caused by the etching residue 36, as shown in FIG. 12, Patent Document 1 describes a configuration in which a protruding portion 37 that has a shape similar to the first wiring line is provided between a plurality of second wiring lines 35 that are disposed over a level difference section made by the first wiring line 33. With this configuration, the level difference section above the first wiring line 33 can be made longer, and the possibility that the etching residue of the second wiring lines 35 are connected, resulting in a short circuit, can be reduced, thereby achieving an effective semiconductor device.